The semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs. As this progression takes place, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as fin-like multigate field effect transistors (FinFET, multigate, triage, gate-all-around devices). The use of multigate (FinFET) devices has been gaining popularity in the semiconductor industry. FinFET devices offer several advantages over traditional Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) devices (also referred to as planar devices). These advantages may include better chip area efficiency, improved carrier mobility, improved speed/energy efficiency, and fabrication processing that is compatible with the fabrication processing of planar devices. Thus, it may be desirable to design an integrated circuit (IC) chip using FinFET devices for a portion of, or the entire IC chip.
A typical FinFET device is fabricated with a thin “fin” (or fin-like structure) extending from a substrate. The fin usually includes silicon and forms the body of the transistor device. The channel of the transistor is formed in this vertical fin. A gate is provided over (e.g., wrapping around) the fin. This type of gate allows greater control of the channel. Other advantages of FinFET devices include reduced short channel effect and higher current flow.
For MOSFET or FinFET devices, on state current (“Ion”) and off-state leakage current (“Ioff”) directly depends on threshold voltage of the gate (“Vth”). For high speed switching operation, Vth should be low, which results in high Ion, and at the same time, high Ioff as well. So the lower limit of the Vth is set by the permissible magnitude of Ioff.
On the other hand, for lower power consumption devices, Vth is high, which will lower both Ion and Ioff. The ratio of Ion and Ioff is known as figure of merit for MOSFETs and higher value of Ion/Ioff is desirable because high Ion would result in higher current drive and lower Ioff would result in low static power dissipation.
Although one cannot obtain high Ion and low Ioff at the same time with the current supply voltages (which have been reduced to reduce dynamic power consumption), and therefore, has to pick either a high Ion or a low Ioff for different transistors, depending on specific needs (speed or low-power), it is desirable if a single chip has all high-speed (low Vth), lower consumption (medium Vth), and low standby power (high Vth) devices in it. High speed devices would consume more energy but provide lots of current for data paths where speed performance is needed, while low standby power is important for mobile devices (memory, etc.). For that, circuit designers would want a scheme of easily obtaining full “palette” of Vths to choose from.
There have been various attempts to control or tune Vth by changing the work function of a gate stack, which is usually a constant for a given device. One of such attempts is to adjust doping by using high doping concentrations in the gate material, and thereby change work function. Polysilicon has been used for such doping. Polysilicon, however, is not favorable as gate material for smaller dimension, or short channel devices because of its high thermal budget process, degradation due to the gate depletion of the doped polysilicon, and dopant penetration problems. Further, Vth can be tuned through doping the channel region, but this typically introduces variability problem known as random-doping fluctuations (“RDF”) and reduction of mobility of channel carriers. As an alternative for obtaining a different range of Vth, metal layers coupled with the use of high-k dielectric came to be used in place of polysilicon. This alternative, however, has also its own shortcomings that the using different gate metal to achieve different Vth values layers greatly increases process complexity and cost.
Therefore, there is a need to provide a method for fabricating a semiconductor device, such as a FinFET, where a wide range of gate threshold voltage can be obtained by varying workfunctions of gate materials with ease, and without the shortcomings associated with the current art described above.